Name		Name	Last commit message	Last commit date
Simulation		Simulation
emulation		emulation
.DS_Store		.DS_Store
Readme.md		Readme.md
Report.pdf		Report.pdf
emulation.tar.gz		emulation.tar.gz

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Course

ECE 571

Project Title

DDR3 Controller Design and Verification

Instructor

Roy Kravitz

Getting Started

All Primary Source codes are in Simulation folder. Please Review these codes.

Running the tests

Re-direct to Simulation folder. -> Makefile --> make all (For Full Compilation and Running the test)

Authors

Teja - Architecture and RTL Design
Tejas - Emulation and Verification
Suraj - RTL Design and Verification
Rahul - RTL Design and Verification

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