Alveo Versal Example Design

TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

NVMe P2P Driver IP for FPGA, written in Bluespec SystemVerilog, with integration examples.

NVMe Queue Driver module for FPGA, written in Bluespec SystemVerilog.

AIPerf is a comprehensive benchmarking tool that measures the performance of generative AI models served by your preferred inference solution.

A comprehensive repository for Compute Express Link (CXL) resources: covering research papers, specifications, simulation/emulation tools, and benchmarks for Type 1, 2, and 3 devices.

OCEAN – Open-source CXL Emulation at Hyperscale Architecture and Networking.

[DATE'25, ICCAD'25] An embedded FPGA-based LLM accelerator capable of supporting Llama2-7B

An open-source simulator framework for neural processing units

a mini 2x2 systolic array and PE demo

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A FPGA friendly 32 bit RISC-V CPU implementation

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Accelerator RTL inspired by VEGETA [HPCA'23] and MicroScopiQ [ISCA'25]

Small footprint and configurable PCIe core

The official repository for the gem5 computer-system architecture simulator.

Spike, a RISC-V ISA Simulator

Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)

A machine learning accelerator core designed for energy-efficient AI at the edge.

Rocket Chip Generator

MQSim is a fast & accurate simulator for modern multi-queue (MQ) and SATA SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and full end-to-end…

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Verilog evaluation benchmark for large language model

A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

A reference book on System-on-Chip Design